The present invention relates to synchronizing signals between multiple devices and more specifically to synchronizing signals using spread spectrum techniques.
Systems that include multiple electronic devices, such as the centrally controlled multiple digital-to-analog converter (DAC) system as shown in FIG. 1, require data signal synchronization. Generally, these multi-device systems include multiple data outputs OUT 1, OUT 2, OUT 3, that need to operate within tight timing constraints. As a result, the system includes both a clock circuit CLOCK SOURCE and a separate synchronization signal distributor SYNC DIST for synchronizing the clock signal. The synchronization signal distributor SYNC DIST receives a synchronization signal SYNC_O from master DAC 1, and distributes it to all slaves DAC 2, DAC 3, at their synchronization signal inputs SYNC_I. In certain prior art embodiments, a synchronization signal distributor is used because LVDS is a point-to-point bus, and unlike a CMOS bus, it cannot broadcast directly from one output to many inputs. Using this distribution system, the synchronization signal distributor SYNC DIST confirms that all of the DACs are in sync and the data out signals are operating within the timing constraints. However, as clock frequencies increase, generating signals that need to occur simultaneously within several devices becomes more difficult due to sampling noise and jitter affects on signal edges. Due to jitter and sampling noise, the DACs may inaccurately read the synchronization and data signals.
In the prior art system shown in FIG. 1, DACs 1, 2, and 3 are identical because they are the same product. Each DAC includes two state machines. State machine #1 is controlled by SYNC_I, and state machine #2 sends its state variable to SYNC_O if it is enabled. For DAC 1, state machine #1 is the working state machine, but state machine #2 is also enabled. DAC1 is the “master” device only because its state machine #2 is enabled and its SYNC_O is connected to the sync distributor. DACs 2 and 3 are “slave” devices because their state machines #2 are disabled. In total there are four state machines active—one master state machine and three slave state machines. The master state machine is not going to be strictly in sync with the slave state machines because of propagation delays on the path, but the goal is to make sure all slave state machines are in sync with each other.